1. Technical Field
The present invention relates generally to semiconductor memory devices and, in particular, to a redundancy circuit for a semiconductor memory device, the redundancy circuit for replacing failed main memory cells with redundancy memory cells according to the type of failure(s) experienced by the main memory cells.
2. Background Description
Currently, a trend exists of reducing the size of electronic products while increasing their functionality. The size minimization and functionality improvement of electronic products is greatly affected by the rapid developments in semiconductor memory devices, which become smaller in size while being imparted with increased functionality. However, such semiconductor memory devices require technologies to integrate a variety of functions and to minimize the occurrence of defects or contamination of the devices during manufacturing processes. Even when the occurrence of defects and contamination are regarded as important factors in determining the yield and the basic manufacturing cost of products, solving such problems is still very difficult. A redundancy circuit is used as a method to solve the problem of reduction in the yield of products resulting from occurrence of defects and contamination of the semiconductor memory device. Such a redundancy circuit plays a more important role in increasing the integration of a semiconductor memory device. Therefore, it is necessary to effectively reduce the occurrence of defects in a semiconductor memory device by using a redundancy circuit.
FIG. 1 is a diagram illustrating a method for making a unit repair of a single row in a semiconductor memory device, according to the prior art. That is, only a single row is repaired at one time. In a redundancy device such as that shown in FIG. 1, each redundancy pre-decoder replaces one row of redundancy cells. In other words, if a memory cell is defective, a row having the defective memory cell is replaced with a row of redundancy memory cells.
FIG. 2 is a diagram illustrating a conventional method for making a unit repair of two rows in a semiconductor memory device, according to the prior art. That is, one redundancy pre-decoder replaces two rows of redundancy cells. In other words, if a memory cell is defective, then one row having the defective memory cell and its neighboring row of normal memory cells are replaced with two rows of redundancy memory cells. The conventional repair method shown in FIG. 2 has an advantage in that any defect occurring at two neighboring rows can be repaired by one redundancy pre-decoder.
FIG. 3 is a diagram illustrating a conventional method for making a unit repair of four rows in a semiconductor memory device, according to the prior art. That is, one redundancy pre-decoder replaces four row rows of redundancy cells. In other words, if a memory cell is defective, then a row having the defective memory cell and its three neighboring rows of memory cells are replaced with four rows of redundancy memory cells. The conventional repair method shown in FIG. 3 has an advantage in that any defect occurring at four rows of memory cells can be repaired by one redundancy pre-decoder.
The conventional repair method illustrated in FIG. 1 has an advantage in that the probability of defects at the redundancy cells is low because the number of redundancy cells to replace defective memory cells is not great. On the contrary, the conventional repair method illustrated in FIG. 1 has a disadvantage in that a plurality of predecoders are needed when a plurality of defects occur at a plurality of neighboring rows.
Also, the conventional repair methods shown in FIGS. 2 and 3 have advantages in that a plurality of memory cells can be replaced by using one redundancy pre-decoder, thereby getting a plurality of defective memory cells to be replaced with neighboring rows of memory cells by one redundancy pre-decoder. However, there is a disadvantage in the aforementioned methods in that neighboring rows are replaced with redundancy rows of memory cells, along with a row having a failed memory cell; thus, the probability of defects occurring at the redundancy cells is increased.
The problems stated above, as well as other related problems of the prior art, are solved by the present invention, a redundancy circuit for a semiconductor memory device. The redundancy circuit replaces failed memory cells with redundancy cells according to the type of failure(s) experienced by the failed memory cells.
According to an aspect of the invention, there is provided a redundancy circuit for a semiconductor memory device having a plurality of normal memory cells. The redundancy circuit includes redundancy memory cells. A redundancy word line decoder has a fuse circuit that includes fuses and an output signal. The output signal is in one of three states depending on input signals. The fuse circuit controls a cutting of the fuses in accordance with the input signals so as to replace defective normal memory cells with the redundancy memory cells depending on a type of defect experienced by the defective normal memory cells.
According to another aspect of the invention, the fuse circuit is constructed to have a one-to-one correspondence to the input signals.
According to yet another aspect of the invention, the fuse circuit includes first, second and third fuses. The fuse circuit generates the output signal to be in the one of three states depending on the cutting of two fuses out of the first, second and third fuses in accordance with the input signals. The three states consist of a logic level that is identical to that of an input signal, a logic level that is opposite to that of the input signal, and a logic level that is unvarying with respect to that of the input signal.
According to still another aspect of the invention, the first and second fuses have first and second ends, respectively. The first ends of the first and second fuses are connected to the output of the fuse circuit.
According to yet still another aspect of the invention, the fuse circuit further includes an inverter for receiving the input signal. A first transistor has a first end, a second end, a third end, and a fourth end, connected to an input signal, a decoder enable control signal, an inverted decoder enable control signal, and the second end of the first fuse, respectively. A second transistor has a first end, a second end, a third end, and a fourth end, connected to an output of the inverter, the inverted decoder enable control signal, the decoder enable control signal, and the second end of the second fuse, respectively.
According to an additional aspect of the invention, there is provided a redundancy circuit for a semiconductor memory. The redundancy circuit includes redundancy memory cells for restoring defective memory cells. A redundancy word line decoder of the redundancy circuit includes a first fuse circuit, a second fuse circuit, and a logic part. The first fuse circuit is constructed with a plurality of fuses that include a first fuse and a second fuse. Each of the plurality of fuses respectively correspond to input signals of a main word line decoder. The first fuse circuit cuts a fuse corresponding to an input signal of the main word line decoder when the redundancy word line decoder is in operation. The second fuse circuit is constructed with another plurality of fuses that include a third fuse, a fourth fuse, and a fifth fuse. Each of the other plurality of fuses respectively correspond to input signals of a sub-word line decoder. The second fuse circuit cuts two fuses out of the third fuse, the fourth fuse, and the fifth fuse according to an input signal of the sub-word line decoder when the redundancy word line decoder is in operation. The first and the second fuse circuits respectively generate output signals in one of three states. The three states consist of a logic level that is identical to that of the input signal of the sub-word line decoder, a logic level that is opposite to that of the input signal of the sub-word line decoder, and a logic level that is unvarying with respect to that of the input signal of the sub-word line decoder. The logic part selects particular redundancy memory cells according to outputs of the first and second fuse circuits, and a redundancy decoder enable control signal.
These and other aspects, features and advantages of the present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.